PI: S N Pradhan Co-PI: Swati Jain

14.8 Lacs INR (20960.50 USD)

Objective of the project was to investigate the use of Digital Signal processorandFPGA as means of Accelerators to desktop machines to increase the throughputofimage processing applications which are required to process large amount ofdata.The main application considered was matching images for generating StereoImages.The operating frequency of the DSP and FPGA devices being less thanthatofprocessors used in PCs, the performance improvement can only be obtainedbyexploiting special architecture of DSPs and possibility of extensive parallelisminFPGA devices. Many cycle accurate simulations were carried out to ascertainthatuseof this devices would give positive gain in the performance in presence of over headsof large amount of data from platform to devices and aggregating theresults.Subtanial gains were observed in this simulations. For implementing algorithmsinFPGA, the approach we used High Level Synthesis language Handel-Cassuchlanguages have less learning curve and can offer developer productivity. SeveralFPGA design evolved during the project. First a hybrid architecture of combiningDSP and FPGA has been designed and simulated performance measured.Hierarchical image matching algorithm, spatial domain correlation algorithms, basicfilter algorithms and FFT based correlation algorithms have been implementedinFPGA during the project work.